Physical Synthesis for Power Under Process Variation

Power is widely considered the only real limiter for Moore’s Law in the next decade [Gelsinger, 2004]. Indeed, IBM CTO B. Meyerson has claimed that CMOS process scaling has already stopped between 130nm and 90nm due to power limitations [Clarke, 2004]. Existing methods for physical synthesis, however, have primarily targeted timing closure and are inadequate to meet the challenge of low-power physical design under process variation. The current lack of a general formulation to simultaneously consider and balance all objectives and constraints leads to potentially gross suboptimality. The goal of the research proposed here is the formulation and implementation of a complete placement-centric physical synthesis flow to minimize total power consumption of an IC design scalably under evolving timing and netlist constraints in the presence of uncertain wire-and-device characteristics. Complete means simultaneous optimization over the following sets of design variables under tight timing constraints.